Hello, I'm Rajesh Sai

Autonomous Humanoid Robot

A biped Robot made using Arduino & Raspberry pi. Ppowered by Alexa/

Equiped with the best in class gyro and motion awarness sensors, this robot is able to maintain balance on its own. Amazon's alexa custom skills were tailored to fine suit this robot for imitating basic human activities.

• Year: 2017
• Type: Project
• Award: 1st - Engineering Clinics Expo 2017

Porting OpenPower A20 Core on FPGA

Implementing A20 core in SoC for embedded processing

Exploring the new opensourced A20 -out of order single threaded optimised core. Implementing it in SoC as Proof of Concept for embedded SoC developement.

• Year: 2021
• Type: Research, Ongoing
• Organisation: C-DAC, Bangalore

Customised hardware acclerator for AI applications using FPGA

Genralised AI acclerator with custom MMU, Cache, Memory controller. Based on RISC-V

Combining the reconfigurable flexibility of the FPGA with the RISC-V ISA. A custom FP32-ALU along with a dedicated matrix multiplication units were designed. Sequential memory accessing is equiped with spatial R/W buffers for virtual cache emulation.
Result: Reconfigurable flexible genralised AI acclerator.

• Year: 2020
• Type: Research, Ongoing

Smart Humanoid Robot

A 5-feet Humanoid Robot with Elevated Sensory System.

Inspired by Google's Project Tango, this robot is equiped with 22 different sensors emulating spatial mapping. Virtual depth maps are perceived. Antonomous navigation, Smart assistant are some of the best features.

• Year: 2018
• Type: Project
• Award: Top 20 - Engineering Clinics Expo 2018

VLSI architecture of DNN Neuron for Facial Recognition

Implementing Alexnet on Zybo Z10 - Zynq7000 FPGA

Feed Forward feural networks are Intensive on Computing. This paper discusses our work on ANN by implementing them on FPGA for facial recognition, results: 1.2x faster inferance

link: Taylor and Francis

• Year: 2019
• Type: Research
• Published: CADEC-2019; Taylor & Francis

System Verilog - UVM Projects

A repository of projects based on System verilog and UVM methodology.

Asorted 15 projects onvarious hardware implementstions and their testbanches written in System Verilog and UVM methodology.

• Year: 2020
• Type: Project
• Link Github

Design and Optimization of Accelerated VLSI architectures for Deep Neural Networks

Implemented in data flow model, this acclerator is built for ResNet-50.

Inspired by Google's TPU, this data flow immplementation of ResNet-50, leverages the reconfigurable DSP blocks of FPGA for faster inferences while consuming much less power compared to a fully implemented model.

link: VIT AP

• Year: 2019
• Type: Research
• Submitted to: SENSE, VIT-AP

E-Doc

An Ambitious tele medicinal kiosk built and developed for rural India.

Co-Developed with Ms.Plabini Jiban Jyothi Nayak, This kiosk aims to eliminate the gab between rural India and the best diagnostic services while linking specalist doctors to remote places.

• Year: 2019
• Type: Project

Cloud Gen-0-rator

A self-sustainable IoT based water buoy with environmental values.

We Designed an autonomous floating buoy system to clear oil spills and accelerate cloud formation. The device analyzes the local conditions and relays data over the cloud.

link: IEEE Xplore

• Year: 2019
• Type: Research, Project
• Award: 1st - Engineering Clinics Expo 2018